The higher the data rate on a DIMM, the higher are the frequencies of the frequency components and the shorter are the physical extents for which this line effect must be taken into account. Present memory developments use data rates which lead to major time-critical problems as a result of the subject under discussion. These present memory module developments have the particular characteristic feature of a central integrated circuit (IC) which is mounted on each DIMM. This integrated circuit (IC) is a memory buffer and produces the electrical signals for communication with the memory modules MMi locally, that is to say on the DIMM.
The Dual in-line memory module (DIMM) comprises a plurality of memory modules (MM) which are formed by DRAM-memory chips mounted on a DIMM circuit board. The DRAM-chips are connected to a memory buffer (HUB) located at the center of the DIMM circuit board. The DRAM-memory modules MMi are connected to the memory buffer by means of the command and address bus (CA) and point to point by a bi-directional data bus (DQ/DS). The data bus comprises for instance 72 parallel data lines. The memory bus is provided for the communication to the micro-controller mounted on a motherboard. The memory buffer is connected to a micro-controller via for instance 12 data lines. The memory buffer performs a parallel/serial data conversion or serial/parallel data conversion for data to be exchanged between DRAM-chips provided on said DIMM module and the motherboard.
The basic DIMM-structure according to the state of the art is shown in FIG. 1. As can be seen, a number of different signals are indicated there, which are either of different length (DQ/DQS) or else are received simultaneously by a large number of memory modules (MMi) over a command and address bus (CA).
Read access to the memory modules MMi of a DIMM is not the only factor affected by this, but is particularly critical. Read access is distinguished by a command being transmitted via the CA bus (Command and Address Bus) to the individual memory modules MMi. This memory modules MMi are formed e.g. by DRAM-integrated circuits. As can be seen without any difficulty, MM4 and MM5 are located closer to the data source (HUB) than the modules MMØ and MM8. It should thus be expected that the read command will reach the memory modules MM4 and MM5 considerably earlier than MMØ and MM8.
The timing diagram shown in FIG. 2 provides an illustration in the form of a graph to this relationship for the MM4 and MMØ.
At time t1, the source (HUB), i.e. the memory buffer, sends the read command via the uni-directional (CA-Bus) to the memory modules MMi. At time t2, this command reaches the memory module MM4. However, since this command is addressed to all the memory modules MMi, a further delay time is required before the final memory module MMØ receives the read command at the time t3. After receiving a read command, a dead time passes before the memory modules MMi start to transmit the data. Since all the memory modules MMi are identical, this dead time is also identical for MMØ and MM4. The dead time T4 at memory module MM4 ends at time t4, and the dead time t0 at the time t6. The memory module MMØ at the distal end of the DIMM waits for the longest dead time TØ to ensure that the all data of the remaining memory modules MMi will reach the memory buffer in time. At these times t4, t6 the memory modules (DRAM) start to transmit the required read data. The response from memory module MM4 reaches the memory buffer at the time t5, but the response from the memory module MMØ does not reach the receiving memory buffer until the time t7. FIG. 2 shows particularly clearly that a read command which is sent at a specific time t1 leads to a considerable time shift AT in the responses (times t5 and t7). If the data rate DR is sufficiently low, that is to say the duration of a single information bit is long in comparison to the time difference ΔT between t5 and t7, then there is no need to take these effects in account. Owing to the ever wider bandwidth required for memory media, this limit is, however, now considerably exceeded.
With increasing data rates DR on the data lines the wave length λ of the data signal is diminished. When the wave length λ reaches the dimension L of a data line dynamic effects on the data line have to be taken into account. The inductance of the line cause skin effect and the high frequency signal is distorted. Consequently dynamic effects cause dynamic time delay variations. These time delay variations have to be compensated to achieve a synchron interface between the DIMM modules and the motherboard.
A method for compensating for different delay times according to the state of the art is to route the interconnects in a meandering shape on the printed circuit board (PCB). However, this conventional method is quite unsuitable for this application. Firstly, the meanders require additional space on the DIMM-PCB, and this is very short. However, a far more serious disadvantage is the fact that the signals do not just have one transmitter and one receiver, but that a number of receivers should be addressed at the same time. This is completely impossible using simple methods since each signal would need to exist two or more times. A signal x which has to be passed from the source to all the memory modules MMi has to exist in versions x0 to x8. Each of these nine signals must then either have no meander at all (for example x0 to MMØ) or has a very large number of meanders (for example x4 to MM4). If the meandering interconnect routing requires additional space, then the additionally required multiplication of each signal leads to insoluble routing problems. Delay time compensation based on the known meandering routing is therefore impossible on a DIMM.